# -*- coding: utf-8 -*-
#
# TARGET arch is: []
# WORD_SIZE is: 8
# POINTER_SIZE is: 8
# LONGDOUBLE_SIZE is: 16
#
import ctypes




_mp_13_0_0_OFFSET_HEADER = True # macro
regMP0_SMN_C2PMSG_32 = 0x0060 # macro
regMP0_SMN_C2PMSG_32_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_33 = 0x0061 # macro
regMP0_SMN_C2PMSG_33_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_34 = 0x0062 # macro
regMP0_SMN_C2PMSG_34_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_35 = 0x0063 # macro
regMP0_SMN_C2PMSG_35_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_36 = 0x0064 # macro
regMP0_SMN_C2PMSG_36_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_37 = 0x0065 # macro
regMP0_SMN_C2PMSG_37_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_38 = 0x0066 # macro
regMP0_SMN_C2PMSG_38_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_39 = 0x0067 # macro
regMP0_SMN_C2PMSG_39_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_40 = 0x0068 # macro
regMP0_SMN_C2PMSG_40_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_41 = 0x0069 # macro
regMP0_SMN_C2PMSG_41_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_42 = 0x006a # macro
regMP0_SMN_C2PMSG_42_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_43 = 0x006b # macro
regMP0_SMN_C2PMSG_43_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_44 = 0x006c # macro
regMP0_SMN_C2PMSG_44_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_45 = 0x006d # macro
regMP0_SMN_C2PMSG_45_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_46 = 0x006e # macro
regMP0_SMN_C2PMSG_46_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_47 = 0x006f # macro
regMP0_SMN_C2PMSG_47_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_48 = 0x0070 # macro
regMP0_SMN_C2PMSG_48_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_49 = 0x0071 # macro
regMP0_SMN_C2PMSG_49_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_50 = 0x0072 # macro
regMP0_SMN_C2PMSG_50_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_51 = 0x0073 # macro
regMP0_SMN_C2PMSG_51_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_52 = 0x0074 # macro
regMP0_SMN_C2PMSG_52_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_53 = 0x0075 # macro
regMP0_SMN_C2PMSG_53_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_54 = 0x0076 # macro
regMP0_SMN_C2PMSG_54_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_55 = 0x0077 # macro
regMP0_SMN_C2PMSG_55_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_56 = 0x0078 # macro
regMP0_SMN_C2PMSG_56_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_57 = 0x0079 # macro
regMP0_SMN_C2PMSG_57_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_58 = 0x007a # macro
regMP0_SMN_C2PMSG_58_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_59 = 0x007b # macro
regMP0_SMN_C2PMSG_59_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_60 = 0x007c # macro
regMP0_SMN_C2PMSG_60_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_61 = 0x007d # macro
regMP0_SMN_C2PMSG_61_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_62 = 0x007e # macro
regMP0_SMN_C2PMSG_62_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_63 = 0x007f # macro
regMP0_SMN_C2PMSG_63_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_64 = 0x0080 # macro
regMP0_SMN_C2PMSG_64_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_65 = 0x0081 # macro
regMP0_SMN_C2PMSG_65_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_66 = 0x0082 # macro
regMP0_SMN_C2PMSG_66_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_67 = 0x0083 # macro
regMP0_SMN_C2PMSG_67_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_68 = 0x0084 # macro
regMP0_SMN_C2PMSG_68_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_69 = 0x0085 # macro
regMP0_SMN_C2PMSG_69_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_70 = 0x0086 # macro
regMP0_SMN_C2PMSG_70_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_71 = 0x0087 # macro
regMP0_SMN_C2PMSG_71_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_72 = 0x0088 # macro
regMP0_SMN_C2PMSG_72_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_73 = 0x0089 # macro
regMP0_SMN_C2PMSG_73_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_74 = 0x008a # macro
regMP0_SMN_C2PMSG_74_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_75 = 0x008b # macro
regMP0_SMN_C2PMSG_75_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_76 = 0x008c # macro
regMP0_SMN_C2PMSG_76_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_77 = 0x008d # macro
regMP0_SMN_C2PMSG_77_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_78 = 0x008e # macro
regMP0_SMN_C2PMSG_78_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_79 = 0x008f # macro
regMP0_SMN_C2PMSG_79_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_80 = 0x0090 # macro
regMP0_SMN_C2PMSG_80_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_81 = 0x0091 # macro
regMP0_SMN_C2PMSG_81_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_82 = 0x0092 # macro
regMP0_SMN_C2PMSG_82_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_83 = 0x0093 # macro
regMP0_SMN_C2PMSG_83_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_84 = 0x0094 # macro
regMP0_SMN_C2PMSG_84_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_85 = 0x0095 # macro
regMP0_SMN_C2PMSG_85_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_86 = 0x0096 # macro
regMP0_SMN_C2PMSG_86_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_87 = 0x0097 # macro
regMP0_SMN_C2PMSG_87_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_88 = 0x0098 # macro
regMP0_SMN_C2PMSG_88_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_89 = 0x0099 # macro
regMP0_SMN_C2PMSG_89_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_90 = 0x009a # macro
regMP0_SMN_C2PMSG_90_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_91 = 0x009b # macro
regMP0_SMN_C2PMSG_91_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_92 = 0x009c # macro
regMP0_SMN_C2PMSG_92_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_93 = 0x009d # macro
regMP0_SMN_C2PMSG_93_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_94 = 0x009e # macro
regMP0_SMN_C2PMSG_94_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_95 = 0x009f # macro
regMP0_SMN_C2PMSG_95_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_96 = 0x00a0 # macro
regMP0_SMN_C2PMSG_96_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_97 = 0x00a1 # macro
regMP0_SMN_C2PMSG_97_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_98 = 0x00a2 # macro
regMP0_SMN_C2PMSG_98_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_99 = 0x00a3 # macro
regMP0_SMN_C2PMSG_99_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_100 = 0x00a4 # macro
regMP0_SMN_C2PMSG_100_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_101 = 0x00a5 # macro
regMP0_SMN_C2PMSG_101_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_102 = 0x00a6 # macro
regMP0_SMN_C2PMSG_102_BASE_IDX = 0 # macro
regMP0_SMN_C2PMSG_103 = 0x00a7 # macro
regMP0_SMN_C2PMSG_103_BASE_IDX = 0 # macro
regMP0_SMN_IH_CREDIT = 0x00c1 # macro
regMP0_SMN_IH_CREDIT_BASE_IDX = 0 # macro
regMP0_SMN_IH_SW_INT = 0x00c2 # macro
regMP0_SMN_IH_SW_INT_BASE_IDX = 0 # macro
regMP0_SMN_IH_SW_INT_CTRL = 0x00c3 # macro
regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_32 = 0x0260 # macro
regMP1_SMN_C2PMSG_32_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_33 = 0x0261 # macro
regMP1_SMN_C2PMSG_33_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_34 = 0x0262 # macro
regMP1_SMN_C2PMSG_34_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_35 = 0x0263 # macro
regMP1_SMN_C2PMSG_35_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_36 = 0x0264 # macro
regMP1_SMN_C2PMSG_36_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_37 = 0x0265 # macro
regMP1_SMN_C2PMSG_37_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_38 = 0x0266 # macro
regMP1_SMN_C2PMSG_38_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_39 = 0x0267 # macro
regMP1_SMN_C2PMSG_39_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_40 = 0x0268 # macro
regMP1_SMN_C2PMSG_40_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_41 = 0x0269 # macro
regMP1_SMN_C2PMSG_41_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_42 = 0x026a # macro
regMP1_SMN_C2PMSG_42_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_43 = 0x026b # macro
regMP1_SMN_C2PMSG_43_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_44 = 0x026c # macro
regMP1_SMN_C2PMSG_44_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_45 = 0x026d # macro
regMP1_SMN_C2PMSG_45_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_46 = 0x026e # macro
regMP1_SMN_C2PMSG_46_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_47 = 0x026f # macro
regMP1_SMN_C2PMSG_47_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_48 = 0x0270 # macro
regMP1_SMN_C2PMSG_48_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_49 = 0x0271 # macro
regMP1_SMN_C2PMSG_49_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_50 = 0x0272 # macro
regMP1_SMN_C2PMSG_50_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_51 = 0x0273 # macro
regMP1_SMN_C2PMSG_51_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_52 = 0x0274 # macro
regMP1_SMN_C2PMSG_52_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_53 = 0x0275 # macro
regMP1_SMN_C2PMSG_53_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_54 = 0x0276 # macro
regMP1_SMN_C2PMSG_54_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_55 = 0x0277 # macro
regMP1_SMN_C2PMSG_55_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_56 = 0x0278 # macro
regMP1_SMN_C2PMSG_56_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_57 = 0x0279 # macro
regMP1_SMN_C2PMSG_57_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_58 = 0x027a # macro
regMP1_SMN_C2PMSG_58_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_59 = 0x027b # macro
regMP1_SMN_C2PMSG_59_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_60 = 0x027c # macro
regMP1_SMN_C2PMSG_60_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_61 = 0x027d # macro
regMP1_SMN_C2PMSG_61_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_62 = 0x027e # macro
regMP1_SMN_C2PMSG_62_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_63 = 0x027f # macro
regMP1_SMN_C2PMSG_63_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_64 = 0x0280 # macro
regMP1_SMN_C2PMSG_64_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_65 = 0x0281 # macro
regMP1_SMN_C2PMSG_65_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_66 = 0x0282 # macro
regMP1_SMN_C2PMSG_66_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_67 = 0x0283 # macro
regMP1_SMN_C2PMSG_67_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_68 = 0x0284 # macro
regMP1_SMN_C2PMSG_68_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_69 = 0x0285 # macro
regMP1_SMN_C2PMSG_69_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_70 = 0x0286 # macro
regMP1_SMN_C2PMSG_70_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_71 = 0x0287 # macro
regMP1_SMN_C2PMSG_71_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_72 = 0x0288 # macro
regMP1_SMN_C2PMSG_72_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_73 = 0x0289 # macro
regMP1_SMN_C2PMSG_73_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_74 = 0x028a # macro
regMP1_SMN_C2PMSG_74_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_75 = 0x028b # macro
regMP1_SMN_C2PMSG_75_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_76 = 0x028c # macro
regMP1_SMN_C2PMSG_76_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_77 = 0x028d # macro
regMP1_SMN_C2PMSG_77_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_78 = 0x028e # macro
regMP1_SMN_C2PMSG_78_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_79 = 0x028f # macro
regMP1_SMN_C2PMSG_79_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_80 = 0x0290 # macro
regMP1_SMN_C2PMSG_80_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_81 = 0x0291 # macro
regMP1_SMN_C2PMSG_81_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_82 = 0x0292 # macro
regMP1_SMN_C2PMSG_82_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_83 = 0x0293 # macro
regMP1_SMN_C2PMSG_83_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_84 = 0x0294 # macro
regMP1_SMN_C2PMSG_84_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_85 = 0x0295 # macro
regMP1_SMN_C2PMSG_85_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_86 = 0x0296 # macro
regMP1_SMN_C2PMSG_86_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_87 = 0x0297 # macro
regMP1_SMN_C2PMSG_87_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_88 = 0x0298 # macro
regMP1_SMN_C2PMSG_88_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_89 = 0x0299 # macro
regMP1_SMN_C2PMSG_89_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_90 = 0x029a # macro
regMP1_SMN_C2PMSG_90_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_91 = 0x029b # macro
regMP1_SMN_C2PMSG_91_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_92 = 0x029c # macro
regMP1_SMN_C2PMSG_92_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_93 = 0x029d # macro
regMP1_SMN_C2PMSG_93_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_94 = 0x029e # macro
regMP1_SMN_C2PMSG_94_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_95 = 0x029f # macro
regMP1_SMN_C2PMSG_95_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_96 = 0x02a0 # macro
regMP1_SMN_C2PMSG_96_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_97 = 0x02a1 # macro
regMP1_SMN_C2PMSG_97_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_98 = 0x02a2 # macro
regMP1_SMN_C2PMSG_98_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_99 = 0x02a3 # macro
regMP1_SMN_C2PMSG_99_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_100 = 0x02a4 # macro
regMP1_SMN_C2PMSG_100_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_101 = 0x02a5 # macro
regMP1_SMN_C2PMSG_101_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_102 = 0x02a6 # macro
regMP1_SMN_C2PMSG_102_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_103 = 0x02a7 # macro
regMP1_SMN_C2PMSG_103_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_104 = 0x02a8 # macro
regMP1_SMN_C2PMSG_104_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_105 = 0x02a9 # macro
regMP1_SMN_C2PMSG_105_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_106 = 0x02aa # macro
regMP1_SMN_C2PMSG_106_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_107 = 0x02ab # macro
regMP1_SMN_C2PMSG_107_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_108 = 0x02ac # macro
regMP1_SMN_C2PMSG_108_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_109 = 0x02ad # macro
regMP1_SMN_C2PMSG_109_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_110 = 0x02ae # macro
regMP1_SMN_C2PMSG_110_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_111 = 0x02af # macro
regMP1_SMN_C2PMSG_111_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_112 = 0x02b0 # macro
regMP1_SMN_C2PMSG_112_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_113 = 0x02b1 # macro
regMP1_SMN_C2PMSG_113_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_114 = 0x02b2 # macro
regMP1_SMN_C2PMSG_114_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_115 = 0x02b3 # macro
regMP1_SMN_C2PMSG_115_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_116 = 0x02b4 # macro
regMP1_SMN_C2PMSG_116_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_117 = 0x02b5 # macro
regMP1_SMN_C2PMSG_117_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_118 = 0x02b6 # macro
regMP1_SMN_C2PMSG_118_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_119 = 0x02b7 # macro
regMP1_SMN_C2PMSG_119_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_120 = 0x02b8 # macro
regMP1_SMN_C2PMSG_120_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_121 = 0x02b9 # macro
regMP1_SMN_C2PMSG_121_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_122 = 0x02ba # macro
regMP1_SMN_C2PMSG_122_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_123 = 0x02bb # macro
regMP1_SMN_C2PMSG_123_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_124 = 0x02bc # macro
regMP1_SMN_C2PMSG_124_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_125 = 0x02bd # macro
regMP1_SMN_C2PMSG_125_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_126 = 0x02be # macro
regMP1_SMN_C2PMSG_126_BASE_IDX = 0 # macro
regMP1_SMN_C2PMSG_127 = 0x02bf # macro
regMP1_SMN_C2PMSG_127_BASE_IDX = 0 # macro
regMP1_SMN_IH_CREDIT = 0x02c1 # macro
regMP1_SMN_IH_CREDIT_BASE_IDX = 0 # macro
regMP1_SMN_IH_SW_INT = 0x02c2 # macro
regMP1_SMN_IH_SW_INT_BASE_IDX = 0 # macro
regMP1_SMN_IH_SW_INT_CTRL = 0x02c3 # macro
regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX = 0 # macro
regMP1_SMN_FPS_CNT = 0x02c4 # macro
regMP1_SMN_FPS_CNT_BASE_IDX = 0 # macro
regMP1_SMN_PUB_CTRL = 0x02c5 # macro
regMP1_SMN_PUB_CTRL_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH0 = 0x0340 # macro
regMP1_SMN_EXT_SCRATCH0_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH1 = 0x0341 # macro
regMP1_SMN_EXT_SCRATCH1_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH2 = 0x0342 # macro
regMP1_SMN_EXT_SCRATCH2_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH3 = 0x0343 # macro
regMP1_SMN_EXT_SCRATCH3_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH4 = 0x0344 # macro
regMP1_SMN_EXT_SCRATCH4_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH5 = 0x0345 # macro
regMP1_SMN_EXT_SCRATCH5_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH6 = 0x0346 # macro
regMP1_SMN_EXT_SCRATCH6_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH7 = 0x0347 # macro
regMP1_SMN_EXT_SCRATCH7_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH8 = 0x0348 # macro
regMP1_SMN_EXT_SCRATCH8_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH10 = 0x034a # macro
regMP1_SMN_EXT_SCRATCH10_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH11 = 0x034b # macro
regMP1_SMN_EXT_SCRATCH11_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH12 = 0x034c # macro
regMP1_SMN_EXT_SCRATCH12_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH13 = 0x034d # macro
regMP1_SMN_EXT_SCRATCH13_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH14 = 0x034e # macro
regMP1_SMN_EXT_SCRATCH14_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH15 = 0x034f # macro
regMP1_SMN_EXT_SCRATCH15_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH16 = 0x0350 # macro
regMP1_SMN_EXT_SCRATCH16_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH17 = 0x0351 # macro
regMP1_SMN_EXT_SCRATCH17_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH18 = 0x0352 # macro
regMP1_SMN_EXT_SCRATCH18_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH19 = 0x0353 # macro
regMP1_SMN_EXT_SCRATCH19_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH20 = 0x0354 # macro
regMP1_SMN_EXT_SCRATCH20_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH21 = 0x0355 # macro
regMP1_SMN_EXT_SCRATCH21_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH22 = 0x0356 # macro
regMP1_SMN_EXT_SCRATCH22_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH23 = 0x0357 # macro
regMP1_SMN_EXT_SCRATCH23_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH24 = 0x0358 # macro
regMP1_SMN_EXT_SCRATCH24_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH25 = 0x0359 # macro
regMP1_SMN_EXT_SCRATCH25_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH26 = 0x035a # macro
regMP1_SMN_EXT_SCRATCH26_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH27 = 0x035b # macro
regMP1_SMN_EXT_SCRATCH27_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH28 = 0x035c # macro
regMP1_SMN_EXT_SCRATCH28_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH29 = 0x035d # macro
regMP1_SMN_EXT_SCRATCH29_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH30 = 0x035e # macro
regMP1_SMN_EXT_SCRATCH30_BASE_IDX = 0 # macro
regMP1_SMN_EXT_SCRATCH31 = 0x035f # macro
regMP1_SMN_EXT_SCRATCH31_BASE_IDX = 0 # macro
regMP1_FIRMWARE_FLAGS = 0xbee009 # macro
regMP1_FIRMWARE_FLAGS_BASE_IDX = 0 # macro
regMPIO_FIRMWARE_FLAGS = 0xbee009 # macro
regMPIO_FIRMWARE_FLAGS_BASE_IDX = 0 # macro
_mp_13_0_0_SH_MASK_HEADER = True # macro
MP0_SMN_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro
MP0_SMN_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro
MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro
MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro
MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro
MP0_SMN_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro
MP0_SMN_IH_SW_INT__ID__SHIFT = 0x0 # macro
MP0_SMN_IH_SW_INT__VALID__SHIFT = 0x8 # macro
MP0_SMN_IH_SW_INT__ID_MASK = 0x000000FF # macro
MP0_SMN_IH_SW_INT__VALID_MASK = 0x00000100 # macro
MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro
MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro
MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro
MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro
MP1_SMN_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_104__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_104__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_105__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_105__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_106__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_106__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_107__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_107__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_108__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_108__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_109__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_109__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_110__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_110__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_111__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_111__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_112__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_112__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_113__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_113__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_114__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_114__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_115__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_115__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_116__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_116__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_117__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_117__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_118__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_118__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_119__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_119__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_120__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_120__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_121__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_121__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_122__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_122__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_123__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_123__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_124__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_124__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_125__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_125__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_126__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_126__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_C2PMSG_127__CONTENT__SHIFT = 0x0 # macro
MP1_SMN_C2PMSG_127__CONTENT_MASK = 0xFFFFFFFF # macro
MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro
MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro
MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro
MP1_SMN_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro
MP1_SMN_IH_SW_INT__ID__SHIFT = 0x0 # macro
MP1_SMN_IH_SW_INT__VALID__SHIFT = 0x8 # macro
MP1_SMN_IH_SW_INT__ID_MASK = 0x000000FF # macro
MP1_SMN_IH_SW_INT__VALID_MASK = 0x00000100 # macro
MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro
MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro
MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro
MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro
MP1_SMN_FPS_CNT__COUNT__SHIFT = 0x0 # macro
MP1_SMN_FPS_CNT__COUNT_MASK = 0xFFFFFFFF # macro
MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT = 0x0 # macro
MP1_SMN_PUB_CTRL__LX3_RESET_MASK = 0x00000001 # macro
MP1_SMN_EXT_SCRATCH0__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH0__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH1__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH1__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH2__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH2__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH3__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH3__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH4__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH4__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH5__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH5__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH6__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH6__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH7__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH7__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH8__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH8__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH10__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH10__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH11__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH11__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH12__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH12__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH13__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH13__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH14__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH14__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH15__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH15__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH16__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH16__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH17__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH17__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH18__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH18__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH19__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH19__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH20__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH20__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH21__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH21__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH22__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH22__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH23__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH23__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH24__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH24__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH25__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH25__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH26__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH26__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH27__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH27__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH28__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH28__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH29__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH29__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH30__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH30__DATA_MASK = 0xFFFFFFFF # macro
MP1_SMN_EXT_SCRATCH31__DATA__SHIFT = 0x0 # macro
MP1_SMN_EXT_SCRATCH31__DATA_MASK = 0xFFFFFFFF # macro
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT = 0x0 # macro
MP1_FIRMWARE_FLAGS__RESERVED__SHIFT = 0x1 # macro
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK = 0x00000001 # macro
MP1_FIRMWARE_FLAGS__RESERVED_MASK = 0xFFFFFFFE # macro
MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT = 0x0 # macro
MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT = 0x1 # macro
MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK = 0x00000001 # macro
MPIO_FIRMWARE_FLAGS__RESERVED_MASK = 0xFFFFFFFE # macro
__all__ = \
    ['MP0_SMN_C2PMSG_100__CONTENT_MASK',
    'MP0_SMN_C2PMSG_100__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_101__CONTENT_MASK',
    'MP0_SMN_C2PMSG_101__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_102__CONTENT_MASK',
    'MP0_SMN_C2PMSG_102__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_103__CONTENT_MASK',
    'MP0_SMN_C2PMSG_103__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_32__CONTENT_MASK',
    'MP0_SMN_C2PMSG_32__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_33__CONTENT_MASK',
    'MP0_SMN_C2PMSG_33__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_34__CONTENT_MASK',
    'MP0_SMN_C2PMSG_34__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_35__CONTENT_MASK',
    'MP0_SMN_C2PMSG_35__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_36__CONTENT_MASK',
    'MP0_SMN_C2PMSG_36__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_37__CONTENT_MASK',
    'MP0_SMN_C2PMSG_37__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_38__CONTENT_MASK',
    'MP0_SMN_C2PMSG_38__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_39__CONTENT_MASK',
    'MP0_SMN_C2PMSG_39__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_40__CONTENT_MASK',
    'MP0_SMN_C2PMSG_40__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_41__CONTENT_MASK',
    'MP0_SMN_C2PMSG_41__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_42__CONTENT_MASK',
    'MP0_SMN_C2PMSG_42__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_43__CONTENT_MASK',
    'MP0_SMN_C2PMSG_43__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_44__CONTENT_MASK',
    'MP0_SMN_C2PMSG_44__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_45__CONTENT_MASK',
    'MP0_SMN_C2PMSG_45__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_46__CONTENT_MASK',
    'MP0_SMN_C2PMSG_46__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_47__CONTENT_MASK',
    'MP0_SMN_C2PMSG_47__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_48__CONTENT_MASK',
    'MP0_SMN_C2PMSG_48__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_49__CONTENT_MASK',
    'MP0_SMN_C2PMSG_49__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_50__CONTENT_MASK',
    'MP0_SMN_C2PMSG_50__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_51__CONTENT_MASK',
    'MP0_SMN_C2PMSG_51__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_52__CONTENT_MASK',
    'MP0_SMN_C2PMSG_52__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_53__CONTENT_MASK',
    'MP0_SMN_C2PMSG_53__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_54__CONTENT_MASK',
    'MP0_SMN_C2PMSG_54__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_55__CONTENT_MASK',
    'MP0_SMN_C2PMSG_55__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_56__CONTENT_MASK',
    'MP0_SMN_C2PMSG_56__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_57__CONTENT_MASK',
    'MP0_SMN_C2PMSG_57__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_58__CONTENT_MASK',
    'MP0_SMN_C2PMSG_58__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_59__CONTENT_MASK',
    'MP0_SMN_C2PMSG_59__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_60__CONTENT_MASK',
    'MP0_SMN_C2PMSG_60__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_61__CONTENT_MASK',
    'MP0_SMN_C2PMSG_61__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_62__CONTENT_MASK',
    'MP0_SMN_C2PMSG_62__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_63__CONTENT_MASK',
    'MP0_SMN_C2PMSG_63__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_64__CONTENT_MASK',
    'MP0_SMN_C2PMSG_64__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_65__CONTENT_MASK',
    'MP0_SMN_C2PMSG_65__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_66__CONTENT_MASK',
    'MP0_SMN_C2PMSG_66__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_67__CONTENT_MASK',
    'MP0_SMN_C2PMSG_67__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_68__CONTENT_MASK',
    'MP0_SMN_C2PMSG_68__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_69__CONTENT_MASK',
    'MP0_SMN_C2PMSG_69__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_70__CONTENT_MASK',
    'MP0_SMN_C2PMSG_70__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_71__CONTENT_MASK',
    'MP0_SMN_C2PMSG_71__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_72__CONTENT_MASK',
    'MP0_SMN_C2PMSG_72__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_73__CONTENT_MASK',
    'MP0_SMN_C2PMSG_73__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_74__CONTENT_MASK',
    'MP0_SMN_C2PMSG_74__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_75__CONTENT_MASK',
    'MP0_SMN_C2PMSG_75__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_76__CONTENT_MASK',
    'MP0_SMN_C2PMSG_76__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_77__CONTENT_MASK',
    'MP0_SMN_C2PMSG_77__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_78__CONTENT_MASK',
    'MP0_SMN_C2PMSG_78__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_79__CONTENT_MASK',
    'MP0_SMN_C2PMSG_79__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_80__CONTENT_MASK',
    'MP0_SMN_C2PMSG_80__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_81__CONTENT_MASK',
    'MP0_SMN_C2PMSG_81__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_82__CONTENT_MASK',
    'MP0_SMN_C2PMSG_82__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_83__CONTENT_MASK',
    'MP0_SMN_C2PMSG_83__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_84__CONTENT_MASK',
    'MP0_SMN_C2PMSG_84__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_85__CONTENT_MASK',
    'MP0_SMN_C2PMSG_85__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_86__CONTENT_MASK',
    'MP0_SMN_C2PMSG_86__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_87__CONTENT_MASK',
    'MP0_SMN_C2PMSG_87__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_88__CONTENT_MASK',
    'MP0_SMN_C2PMSG_88__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_89__CONTENT_MASK',
    'MP0_SMN_C2PMSG_89__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_90__CONTENT_MASK',
    'MP0_SMN_C2PMSG_90__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_91__CONTENT_MASK',
    'MP0_SMN_C2PMSG_91__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_92__CONTENT_MASK',
    'MP0_SMN_C2PMSG_92__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_93__CONTENT_MASK',
    'MP0_SMN_C2PMSG_93__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_94__CONTENT_MASK',
    'MP0_SMN_C2PMSG_94__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_95__CONTENT_MASK',
    'MP0_SMN_C2PMSG_95__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_96__CONTENT_MASK',
    'MP0_SMN_C2PMSG_96__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_97__CONTENT_MASK',
    'MP0_SMN_C2PMSG_97__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_98__CONTENT_MASK',
    'MP0_SMN_C2PMSG_98__CONTENT__SHIFT',
    'MP0_SMN_C2PMSG_99__CONTENT_MASK',
    'MP0_SMN_C2PMSG_99__CONTENT__SHIFT',
    'MP0_SMN_IH_CREDIT__CLIENT_ID_MASK',
    'MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT',
    'MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK',
    'MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT',
    'MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK',
    'MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT',
    'MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK',
    'MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT',
    'MP0_SMN_IH_SW_INT__ID_MASK', 'MP0_SMN_IH_SW_INT__ID__SHIFT',
    'MP0_SMN_IH_SW_INT__VALID_MASK',
    'MP0_SMN_IH_SW_INT__VALID__SHIFT',
    'MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK',
    'MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT',
    'MP1_FIRMWARE_FLAGS__RESERVED_MASK',
    'MP1_FIRMWARE_FLAGS__RESERVED__SHIFT',
    'MP1_SMN_C2PMSG_100__CONTENT_MASK',
    'MP1_SMN_C2PMSG_100__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_101__CONTENT_MASK',
    'MP1_SMN_C2PMSG_101__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_102__CONTENT_MASK',
    'MP1_SMN_C2PMSG_102__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_103__CONTENT_MASK',
    'MP1_SMN_C2PMSG_103__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_104__CONTENT_MASK',
    'MP1_SMN_C2PMSG_104__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_105__CONTENT_MASK',
    'MP1_SMN_C2PMSG_105__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_106__CONTENT_MASK',
    'MP1_SMN_C2PMSG_106__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_107__CONTENT_MASK',
    'MP1_SMN_C2PMSG_107__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_108__CONTENT_MASK',
    'MP1_SMN_C2PMSG_108__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_109__CONTENT_MASK',
    'MP1_SMN_C2PMSG_109__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_110__CONTENT_MASK',
    'MP1_SMN_C2PMSG_110__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_111__CONTENT_MASK',
    'MP1_SMN_C2PMSG_111__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_112__CONTENT_MASK',
    'MP1_SMN_C2PMSG_112__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_113__CONTENT_MASK',
    'MP1_SMN_C2PMSG_113__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_114__CONTENT_MASK',
    'MP1_SMN_C2PMSG_114__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_115__CONTENT_MASK',
    'MP1_SMN_C2PMSG_115__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_116__CONTENT_MASK',
    'MP1_SMN_C2PMSG_116__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_117__CONTENT_MASK',
    'MP1_SMN_C2PMSG_117__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_118__CONTENT_MASK',
    'MP1_SMN_C2PMSG_118__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_119__CONTENT_MASK',
    'MP1_SMN_C2PMSG_119__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_120__CONTENT_MASK',
    'MP1_SMN_C2PMSG_120__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_121__CONTENT_MASK',
    'MP1_SMN_C2PMSG_121__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_122__CONTENT_MASK',
    'MP1_SMN_C2PMSG_122__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_123__CONTENT_MASK',
    'MP1_SMN_C2PMSG_123__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_124__CONTENT_MASK',
    'MP1_SMN_C2PMSG_124__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_125__CONTENT_MASK',
    'MP1_SMN_C2PMSG_125__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_126__CONTENT_MASK',
    'MP1_SMN_C2PMSG_126__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_127__CONTENT_MASK',
    'MP1_SMN_C2PMSG_127__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_32__CONTENT_MASK',
    'MP1_SMN_C2PMSG_32__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_33__CONTENT_MASK',
    'MP1_SMN_C2PMSG_33__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_34__CONTENT_MASK',
    'MP1_SMN_C2PMSG_34__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_35__CONTENT_MASK',
    'MP1_SMN_C2PMSG_35__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_36__CONTENT_MASK',
    'MP1_SMN_C2PMSG_36__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_37__CONTENT_MASK',
    'MP1_SMN_C2PMSG_37__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_38__CONTENT_MASK',
    'MP1_SMN_C2PMSG_38__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_39__CONTENT_MASK',
    'MP1_SMN_C2PMSG_39__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_40__CONTENT_MASK',
    'MP1_SMN_C2PMSG_40__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_41__CONTENT_MASK',
    'MP1_SMN_C2PMSG_41__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_42__CONTENT_MASK',
    'MP1_SMN_C2PMSG_42__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_43__CONTENT_MASK',
    'MP1_SMN_C2PMSG_43__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_44__CONTENT_MASK',
    'MP1_SMN_C2PMSG_44__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_45__CONTENT_MASK',
    'MP1_SMN_C2PMSG_45__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_46__CONTENT_MASK',
    'MP1_SMN_C2PMSG_46__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_47__CONTENT_MASK',
    'MP1_SMN_C2PMSG_47__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_48__CONTENT_MASK',
    'MP1_SMN_C2PMSG_48__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_49__CONTENT_MASK',
    'MP1_SMN_C2PMSG_49__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_50__CONTENT_MASK',
    'MP1_SMN_C2PMSG_50__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_51__CONTENT_MASK',
    'MP1_SMN_C2PMSG_51__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_52__CONTENT_MASK',
    'MP1_SMN_C2PMSG_52__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_53__CONTENT_MASK',
    'MP1_SMN_C2PMSG_53__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_54__CONTENT_MASK',
    'MP1_SMN_C2PMSG_54__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_55__CONTENT_MASK',
    'MP1_SMN_C2PMSG_55__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_56__CONTENT_MASK',
    'MP1_SMN_C2PMSG_56__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_57__CONTENT_MASK',
    'MP1_SMN_C2PMSG_57__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_58__CONTENT_MASK',
    'MP1_SMN_C2PMSG_58__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_59__CONTENT_MASK',
    'MP1_SMN_C2PMSG_59__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_60__CONTENT_MASK',
    'MP1_SMN_C2PMSG_60__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_61__CONTENT_MASK',
    'MP1_SMN_C2PMSG_61__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_62__CONTENT_MASK',
    'MP1_SMN_C2PMSG_62__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_63__CONTENT_MASK',
    'MP1_SMN_C2PMSG_63__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_64__CONTENT_MASK',
    'MP1_SMN_C2PMSG_64__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_65__CONTENT_MASK',
    'MP1_SMN_C2PMSG_65__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_66__CONTENT_MASK',
    'MP1_SMN_C2PMSG_66__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_67__CONTENT_MASK',
    'MP1_SMN_C2PMSG_67__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_68__CONTENT_MASK',
    'MP1_SMN_C2PMSG_68__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_69__CONTENT_MASK',
    'MP1_SMN_C2PMSG_69__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_70__CONTENT_MASK',
    'MP1_SMN_C2PMSG_70__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_71__CONTENT_MASK',
    'MP1_SMN_C2PMSG_71__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_72__CONTENT_MASK',
    'MP1_SMN_C2PMSG_72__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_73__CONTENT_MASK',
    'MP1_SMN_C2PMSG_73__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_74__CONTENT_MASK',
    'MP1_SMN_C2PMSG_74__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_75__CONTENT_MASK',
    'MP1_SMN_C2PMSG_75__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_76__CONTENT_MASK',
    'MP1_SMN_C2PMSG_76__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_77__CONTENT_MASK',
    'MP1_SMN_C2PMSG_77__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_78__CONTENT_MASK',
    'MP1_SMN_C2PMSG_78__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_79__CONTENT_MASK',
    'MP1_SMN_C2PMSG_79__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_80__CONTENT_MASK',
    'MP1_SMN_C2PMSG_80__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_81__CONTENT_MASK',
    'MP1_SMN_C2PMSG_81__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_82__CONTENT_MASK',
    'MP1_SMN_C2PMSG_82__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_83__CONTENT_MASK',
    'MP1_SMN_C2PMSG_83__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_84__CONTENT_MASK',
    'MP1_SMN_C2PMSG_84__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_85__CONTENT_MASK',
    'MP1_SMN_C2PMSG_85__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_86__CONTENT_MASK',
    'MP1_SMN_C2PMSG_86__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_87__CONTENT_MASK',
    'MP1_SMN_C2PMSG_87__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_88__CONTENT_MASK',
    'MP1_SMN_C2PMSG_88__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_89__CONTENT_MASK',
    'MP1_SMN_C2PMSG_89__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_90__CONTENT_MASK',
    'MP1_SMN_C2PMSG_90__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_91__CONTENT_MASK',
    'MP1_SMN_C2PMSG_91__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_92__CONTENT_MASK',
    'MP1_SMN_C2PMSG_92__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_93__CONTENT_MASK',
    'MP1_SMN_C2PMSG_93__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_94__CONTENT_MASK',
    'MP1_SMN_C2PMSG_94__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_95__CONTENT_MASK',
    'MP1_SMN_C2PMSG_95__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_96__CONTENT_MASK',
    'MP1_SMN_C2PMSG_96__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_97__CONTENT_MASK',
    'MP1_SMN_C2PMSG_97__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_98__CONTENT_MASK',
    'MP1_SMN_C2PMSG_98__CONTENT__SHIFT',
    'MP1_SMN_C2PMSG_99__CONTENT_MASK',
    'MP1_SMN_C2PMSG_99__CONTENT__SHIFT',
    'MP1_SMN_EXT_SCRATCH0__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH0__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH10__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH10__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH11__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH11__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH12__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH12__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH13__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH13__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH14__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH14__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH15__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH15__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH16__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH16__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH17__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH17__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH18__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH18__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH19__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH19__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH1__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH1__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH20__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH20__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH21__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH21__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH22__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH22__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH23__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH23__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH24__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH24__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH25__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH25__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH26__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH26__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH27__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH27__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH28__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH28__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH29__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH29__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH2__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH2__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH30__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH30__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH31__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH31__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH3__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH3__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH4__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH4__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH5__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH5__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH6__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH6__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH7__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH7__DATA__SHIFT',
    'MP1_SMN_EXT_SCRATCH8__DATA_MASK',
    'MP1_SMN_EXT_SCRATCH8__DATA__SHIFT',
    'MP1_SMN_FPS_CNT__COUNT_MASK', 'MP1_SMN_FPS_CNT__COUNT__SHIFT',
    'MP1_SMN_IH_CREDIT__CLIENT_ID_MASK',
    'MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT',
    'MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK',
    'MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT',
    'MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK',
    'MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT',
    'MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK',
    'MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT',
    'MP1_SMN_IH_SW_INT__ID_MASK', 'MP1_SMN_IH_SW_INT__ID__SHIFT',
    'MP1_SMN_IH_SW_INT__VALID_MASK',
    'MP1_SMN_IH_SW_INT__VALID__SHIFT',
    'MP1_SMN_PUB_CTRL__LX3_RESET_MASK',
    'MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT',
    'MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK',
    'MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT',
    'MPIO_FIRMWARE_FLAGS__RESERVED_MASK',
    'MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT',
    '_mp_13_0_0_OFFSET_HEADER', '_mp_13_0_0_SH_MASK_HEADER',
    'regMP0_SMN_C2PMSG_100', 'regMP0_SMN_C2PMSG_100_BASE_IDX',
    'regMP0_SMN_C2PMSG_101', 'regMP0_SMN_C2PMSG_101_BASE_IDX',
    'regMP0_SMN_C2PMSG_102', 'regMP0_SMN_C2PMSG_102_BASE_IDX',
    'regMP0_SMN_C2PMSG_103', 'regMP0_SMN_C2PMSG_103_BASE_IDX',
    'regMP0_SMN_C2PMSG_32', 'regMP0_SMN_C2PMSG_32_BASE_IDX',
    'regMP0_SMN_C2PMSG_33', 'regMP0_SMN_C2PMSG_33_BASE_IDX',
    'regMP0_SMN_C2PMSG_34', 'regMP0_SMN_C2PMSG_34_BASE_IDX',
    'regMP0_SMN_C2PMSG_35', 'regMP0_SMN_C2PMSG_35_BASE_IDX',
    'regMP0_SMN_C2PMSG_36', 'regMP0_SMN_C2PMSG_36_BASE_IDX',
    'regMP0_SMN_C2PMSG_37', 'regMP0_SMN_C2PMSG_37_BASE_IDX',
    'regMP0_SMN_C2PMSG_38', 'regMP0_SMN_C2PMSG_38_BASE_IDX',
    'regMP0_SMN_C2PMSG_39', 'regMP0_SMN_C2PMSG_39_BASE_IDX',
    'regMP0_SMN_C2PMSG_40', 'regMP0_SMN_C2PMSG_40_BASE_IDX',
    'regMP0_SMN_C2PMSG_41', 'regMP0_SMN_C2PMSG_41_BASE_IDX',
    'regMP0_SMN_C2PMSG_42', 'regMP0_SMN_C2PMSG_42_BASE_IDX',
    'regMP0_SMN_C2PMSG_43', 'regMP0_SMN_C2PMSG_43_BASE_IDX',
    'regMP0_SMN_C2PMSG_44', 'regMP0_SMN_C2PMSG_44_BASE_IDX',
    'regMP0_SMN_C2PMSG_45', 'regMP0_SMN_C2PMSG_45_BASE_IDX',
    'regMP0_SMN_C2PMSG_46', 'regMP0_SMN_C2PMSG_46_BASE_IDX',
    'regMP0_SMN_C2PMSG_47', 'regMP0_SMN_C2PMSG_47_BASE_IDX',
    'regMP0_SMN_C2PMSG_48', 'regMP0_SMN_C2PMSG_48_BASE_IDX',
    'regMP0_SMN_C2PMSG_49', 'regMP0_SMN_C2PMSG_49_BASE_IDX',
    'regMP0_SMN_C2PMSG_50', 'regMP0_SMN_C2PMSG_50_BASE_IDX',
    'regMP0_SMN_C2PMSG_51', 'regMP0_SMN_C2PMSG_51_BASE_IDX',
    'regMP0_SMN_C2PMSG_52', 'regMP0_SMN_C2PMSG_52_BASE_IDX',
    'regMP0_SMN_C2PMSG_53', 'regMP0_SMN_C2PMSG_53_BASE_IDX',
    'regMP0_SMN_C2PMSG_54', 'regMP0_SMN_C2PMSG_54_BASE_IDX',
    'regMP0_SMN_C2PMSG_55', 'regMP0_SMN_C2PMSG_55_BASE_IDX',
    'regMP0_SMN_C2PMSG_56', 'regMP0_SMN_C2PMSG_56_BASE_IDX',
    'regMP0_SMN_C2PMSG_57', 'regMP0_SMN_C2PMSG_57_BASE_IDX',
    'regMP0_SMN_C2PMSG_58', 'regMP0_SMN_C2PMSG_58_BASE_IDX',
    'regMP0_SMN_C2PMSG_59', 'regMP0_SMN_C2PMSG_59_BASE_IDX',
    'regMP0_SMN_C2PMSG_60', 'regMP0_SMN_C2PMSG_60_BASE_IDX',
    'regMP0_SMN_C2PMSG_61', 'regMP0_SMN_C2PMSG_61_BASE_IDX',
    'regMP0_SMN_C2PMSG_62', 'regMP0_SMN_C2PMSG_62_BASE_IDX',
    'regMP0_SMN_C2PMSG_63', 'regMP0_SMN_C2PMSG_63_BASE_IDX',
    'regMP0_SMN_C2PMSG_64', 'regMP0_SMN_C2PMSG_64_BASE_IDX',
    'regMP0_SMN_C2PMSG_65', 'regMP0_SMN_C2PMSG_65_BASE_IDX',
    'regMP0_SMN_C2PMSG_66', 'regMP0_SMN_C2PMSG_66_BASE_IDX',
    'regMP0_SMN_C2PMSG_67', 'regMP0_SMN_C2PMSG_67_BASE_IDX',
    'regMP0_SMN_C2PMSG_68', 'regMP0_SMN_C2PMSG_68_BASE_IDX',
    'regMP0_SMN_C2PMSG_69', 'regMP0_SMN_C2PMSG_69_BASE_IDX',
    'regMP0_SMN_C2PMSG_70', 'regMP0_SMN_C2PMSG_70_BASE_IDX',
    'regMP0_SMN_C2PMSG_71', 'regMP0_SMN_C2PMSG_71_BASE_IDX',
    'regMP0_SMN_C2PMSG_72', 'regMP0_SMN_C2PMSG_72_BASE_IDX',
    'regMP0_SMN_C2PMSG_73', 'regMP0_SMN_C2PMSG_73_BASE_IDX',
    'regMP0_SMN_C2PMSG_74', 'regMP0_SMN_C2PMSG_74_BASE_IDX',
    'regMP0_SMN_C2PMSG_75', 'regMP0_SMN_C2PMSG_75_BASE_IDX',
    'regMP0_SMN_C2PMSG_76', 'regMP0_SMN_C2PMSG_76_BASE_IDX',
    'regMP0_SMN_C2PMSG_77', 'regMP0_SMN_C2PMSG_77_BASE_IDX',
    'regMP0_SMN_C2PMSG_78', 'regMP0_SMN_C2PMSG_78_BASE_IDX',
    'regMP0_SMN_C2PMSG_79', 'regMP0_SMN_C2PMSG_79_BASE_IDX',
    'regMP0_SMN_C2PMSG_80', 'regMP0_SMN_C2PMSG_80_BASE_IDX',
    'regMP0_SMN_C2PMSG_81', 'regMP0_SMN_C2PMSG_81_BASE_IDX',
    'regMP0_SMN_C2PMSG_82', 'regMP0_SMN_C2PMSG_82_BASE_IDX',
    'regMP0_SMN_C2PMSG_83', 'regMP0_SMN_C2PMSG_83_BASE_IDX',
    'regMP0_SMN_C2PMSG_84', 'regMP0_SMN_C2PMSG_84_BASE_IDX',
    'regMP0_SMN_C2PMSG_85', 'regMP0_SMN_C2PMSG_85_BASE_IDX',
    'regMP0_SMN_C2PMSG_86', 'regMP0_SMN_C2PMSG_86_BASE_IDX',
    'regMP0_SMN_C2PMSG_87', 'regMP0_SMN_C2PMSG_87_BASE_IDX',
    'regMP0_SMN_C2PMSG_88', 'regMP0_SMN_C2PMSG_88_BASE_IDX',
    'regMP0_SMN_C2PMSG_89', 'regMP0_SMN_C2PMSG_89_BASE_IDX',
    'regMP0_SMN_C2PMSG_90', 'regMP0_SMN_C2PMSG_90_BASE_IDX',
    'regMP0_SMN_C2PMSG_91', 'regMP0_SMN_C2PMSG_91_BASE_IDX',
    'regMP0_SMN_C2PMSG_92', 'regMP0_SMN_C2PMSG_92_BASE_IDX',
    'regMP0_SMN_C2PMSG_93', 'regMP0_SMN_C2PMSG_93_BASE_IDX',
    'regMP0_SMN_C2PMSG_94', 'regMP0_SMN_C2PMSG_94_BASE_IDX',
    'regMP0_SMN_C2PMSG_95', 'regMP0_SMN_C2PMSG_95_BASE_IDX',
    'regMP0_SMN_C2PMSG_96', 'regMP0_SMN_C2PMSG_96_BASE_IDX',
    'regMP0_SMN_C2PMSG_97', 'regMP0_SMN_C2PMSG_97_BASE_IDX',
    'regMP0_SMN_C2PMSG_98', 'regMP0_SMN_C2PMSG_98_BASE_IDX',
    'regMP0_SMN_C2PMSG_99', 'regMP0_SMN_C2PMSG_99_BASE_IDX',
    'regMP0_SMN_IH_CREDIT', 'regMP0_SMN_IH_CREDIT_BASE_IDX',
    'regMP0_SMN_IH_SW_INT', 'regMP0_SMN_IH_SW_INT_BASE_IDX',
    'regMP0_SMN_IH_SW_INT_CTRL', 'regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX',
    'regMP1_FIRMWARE_FLAGS', 'regMP1_FIRMWARE_FLAGS_BASE_IDX',
    'regMP1_SMN_C2PMSG_100', 'regMP1_SMN_C2PMSG_100_BASE_IDX',
    'regMP1_SMN_C2PMSG_101', 'regMP1_SMN_C2PMSG_101_BASE_IDX',
    'regMP1_SMN_C2PMSG_102', 'regMP1_SMN_C2PMSG_102_BASE_IDX',
    'regMP1_SMN_C2PMSG_103', 'regMP1_SMN_C2PMSG_103_BASE_IDX',
    'regMP1_SMN_C2PMSG_104', 'regMP1_SMN_C2PMSG_104_BASE_IDX',
    'regMP1_SMN_C2PMSG_105', 'regMP1_SMN_C2PMSG_105_BASE_IDX',
    'regMP1_SMN_C2PMSG_106', 'regMP1_SMN_C2PMSG_106_BASE_IDX',
    'regMP1_SMN_C2PMSG_107', 'regMP1_SMN_C2PMSG_107_BASE_IDX',
    'regMP1_SMN_C2PMSG_108', 'regMP1_SMN_C2PMSG_108_BASE_IDX',
    'regMP1_SMN_C2PMSG_109', 'regMP1_SMN_C2PMSG_109_BASE_IDX',
    'regMP1_SMN_C2PMSG_110', 'regMP1_SMN_C2PMSG_110_BASE_IDX',
    'regMP1_SMN_C2PMSG_111', 'regMP1_SMN_C2PMSG_111_BASE_IDX',
    'regMP1_SMN_C2PMSG_112', 'regMP1_SMN_C2PMSG_112_BASE_IDX',
    'regMP1_SMN_C2PMSG_113', 'regMP1_SMN_C2PMSG_113_BASE_IDX',
    'regMP1_SMN_C2PMSG_114', 'regMP1_SMN_C2PMSG_114_BASE_IDX',
    'regMP1_SMN_C2PMSG_115', 'regMP1_SMN_C2PMSG_115_BASE_IDX',
    'regMP1_SMN_C2PMSG_116', 'regMP1_SMN_C2PMSG_116_BASE_IDX',
    'regMP1_SMN_C2PMSG_117', 'regMP1_SMN_C2PMSG_117_BASE_IDX',
    'regMP1_SMN_C2PMSG_118', 'regMP1_SMN_C2PMSG_118_BASE_IDX',
    'regMP1_SMN_C2PMSG_119', 'regMP1_SMN_C2PMSG_119_BASE_IDX',
    'regMP1_SMN_C2PMSG_120', 'regMP1_SMN_C2PMSG_120_BASE_IDX',
    'regMP1_SMN_C2PMSG_121', 'regMP1_SMN_C2PMSG_121_BASE_IDX',
    'regMP1_SMN_C2PMSG_122', 'regMP1_SMN_C2PMSG_122_BASE_IDX',
    'regMP1_SMN_C2PMSG_123', 'regMP1_SMN_C2PMSG_123_BASE_IDX',
    'regMP1_SMN_C2PMSG_124', 'regMP1_SMN_C2PMSG_124_BASE_IDX',
    'regMP1_SMN_C2PMSG_125', 'regMP1_SMN_C2PMSG_125_BASE_IDX',
    'regMP1_SMN_C2PMSG_126', 'regMP1_SMN_C2PMSG_126_BASE_IDX',
    'regMP1_SMN_C2PMSG_127', 'regMP1_SMN_C2PMSG_127_BASE_IDX',
    'regMP1_SMN_C2PMSG_32', 'regMP1_SMN_C2PMSG_32_BASE_IDX',
    'regMP1_SMN_C2PMSG_33', 'regMP1_SMN_C2PMSG_33_BASE_IDX',
    'regMP1_SMN_C2PMSG_34', 'regMP1_SMN_C2PMSG_34_BASE_IDX',
    'regMP1_SMN_C2PMSG_35', 'regMP1_SMN_C2PMSG_35_BASE_IDX',
    'regMP1_SMN_C2PMSG_36', 'regMP1_SMN_C2PMSG_36_BASE_IDX',
    'regMP1_SMN_C2PMSG_37', 'regMP1_SMN_C2PMSG_37_BASE_IDX',
    'regMP1_SMN_C2PMSG_38', 'regMP1_SMN_C2PMSG_38_BASE_IDX',
    'regMP1_SMN_C2PMSG_39', 'regMP1_SMN_C2PMSG_39_BASE_IDX',
    'regMP1_SMN_C2PMSG_40', 'regMP1_SMN_C2PMSG_40_BASE_IDX',
    'regMP1_SMN_C2PMSG_41', 'regMP1_SMN_C2PMSG_41_BASE_IDX',
    'regMP1_SMN_C2PMSG_42', 'regMP1_SMN_C2PMSG_42_BASE_IDX',
    'regMP1_SMN_C2PMSG_43', 'regMP1_SMN_C2PMSG_43_BASE_IDX',
    'regMP1_SMN_C2PMSG_44', 'regMP1_SMN_C2PMSG_44_BASE_IDX',
    'regMP1_SMN_C2PMSG_45', 'regMP1_SMN_C2PMSG_45_BASE_IDX',
    'regMP1_SMN_C2PMSG_46', 'regMP1_SMN_C2PMSG_46_BASE_IDX',
    'regMP1_SMN_C2PMSG_47', 'regMP1_SMN_C2PMSG_47_BASE_IDX',
    'regMP1_SMN_C2PMSG_48', 'regMP1_SMN_C2PMSG_48_BASE_IDX',
    'regMP1_SMN_C2PMSG_49', 'regMP1_SMN_C2PMSG_49_BASE_IDX',
    'regMP1_SMN_C2PMSG_50', 'regMP1_SMN_C2PMSG_50_BASE_IDX',
    'regMP1_SMN_C2PMSG_51', 'regMP1_SMN_C2PMSG_51_BASE_IDX',
    'regMP1_SMN_C2PMSG_52', 'regMP1_SMN_C2PMSG_52_BASE_IDX',
    'regMP1_SMN_C2PMSG_53', 'regMP1_SMN_C2PMSG_53_BASE_IDX',
    'regMP1_SMN_C2PMSG_54', 'regMP1_SMN_C2PMSG_54_BASE_IDX',
    'regMP1_SMN_C2PMSG_55', 'regMP1_SMN_C2PMSG_55_BASE_IDX',
    'regMP1_SMN_C2PMSG_56', 'regMP1_SMN_C2PMSG_56_BASE_IDX',
    'regMP1_SMN_C2PMSG_57', 'regMP1_SMN_C2PMSG_57_BASE_IDX',
    'regMP1_SMN_C2PMSG_58', 'regMP1_SMN_C2PMSG_58_BASE_IDX',
    'regMP1_SMN_C2PMSG_59', 'regMP1_SMN_C2PMSG_59_BASE_IDX',
    'regMP1_SMN_C2PMSG_60', 'regMP1_SMN_C2PMSG_60_BASE_IDX',
    'regMP1_SMN_C2PMSG_61', 'regMP1_SMN_C2PMSG_61_BASE_IDX',
    'regMP1_SMN_C2PMSG_62', 'regMP1_SMN_C2PMSG_62_BASE_IDX',
    'regMP1_SMN_C2PMSG_63', 'regMP1_SMN_C2PMSG_63_BASE_IDX',
    'regMP1_SMN_C2PMSG_64', 'regMP1_SMN_C2PMSG_64_BASE_IDX',
    'regMP1_SMN_C2PMSG_65', 'regMP1_SMN_C2PMSG_65_BASE_IDX',
    'regMP1_SMN_C2PMSG_66', 'regMP1_SMN_C2PMSG_66_BASE_IDX',
    'regMP1_SMN_C2PMSG_67', 'regMP1_SMN_C2PMSG_67_BASE_IDX',
    'regMP1_SMN_C2PMSG_68', 'regMP1_SMN_C2PMSG_68_BASE_IDX',
    'regMP1_SMN_C2PMSG_69', 'regMP1_SMN_C2PMSG_69_BASE_IDX',
    'regMP1_SMN_C2PMSG_70', 'regMP1_SMN_C2PMSG_70_BASE_IDX',
    'regMP1_SMN_C2PMSG_71', 'regMP1_SMN_C2PMSG_71_BASE_IDX',
    'regMP1_SMN_C2PMSG_72', 'regMP1_SMN_C2PMSG_72_BASE_IDX',
    'regMP1_SMN_C2PMSG_73', 'regMP1_SMN_C2PMSG_73_BASE_IDX',
    'regMP1_SMN_C2PMSG_74', 'regMP1_SMN_C2PMSG_74_BASE_IDX',
    'regMP1_SMN_C2PMSG_75', 'regMP1_SMN_C2PMSG_75_BASE_IDX',
    'regMP1_SMN_C2PMSG_76', 'regMP1_SMN_C2PMSG_76_BASE_IDX',
    'regMP1_SMN_C2PMSG_77', 'regMP1_SMN_C2PMSG_77_BASE_IDX',
    'regMP1_SMN_C2PMSG_78', 'regMP1_SMN_C2PMSG_78_BASE_IDX',
    'regMP1_SMN_C2PMSG_79', 'regMP1_SMN_C2PMSG_79_BASE_IDX',
    'regMP1_SMN_C2PMSG_80', 'regMP1_SMN_C2PMSG_80_BASE_IDX',
    'regMP1_SMN_C2PMSG_81', 'regMP1_SMN_C2PMSG_81_BASE_IDX',
    'regMP1_SMN_C2PMSG_82', 'regMP1_SMN_C2PMSG_82_BASE_IDX',
    'regMP1_SMN_C2PMSG_83', 'regMP1_SMN_C2PMSG_83_BASE_IDX',
    'regMP1_SMN_C2PMSG_84', 'regMP1_SMN_C2PMSG_84_BASE_IDX',
    'regMP1_SMN_C2PMSG_85', 'regMP1_SMN_C2PMSG_85_BASE_IDX',
    'regMP1_SMN_C2PMSG_86', 'regMP1_SMN_C2PMSG_86_BASE_IDX',
    'regMP1_SMN_C2PMSG_87', 'regMP1_SMN_C2PMSG_87_BASE_IDX',
    'regMP1_SMN_C2PMSG_88', 'regMP1_SMN_C2PMSG_88_BASE_IDX',
    'regMP1_SMN_C2PMSG_89', 'regMP1_SMN_C2PMSG_89_BASE_IDX',
    'regMP1_SMN_C2PMSG_90', 'regMP1_SMN_C2PMSG_90_BASE_IDX',
    'regMP1_SMN_C2PMSG_91', 'regMP1_SMN_C2PMSG_91_BASE_IDX',
    'regMP1_SMN_C2PMSG_92', 'regMP1_SMN_C2PMSG_92_BASE_IDX',
    'regMP1_SMN_C2PMSG_93', 'regMP1_SMN_C2PMSG_93_BASE_IDX',
    'regMP1_SMN_C2PMSG_94', 'regMP1_SMN_C2PMSG_94_BASE_IDX',
    'regMP1_SMN_C2PMSG_95', 'regMP1_SMN_C2PMSG_95_BASE_IDX',
    'regMP1_SMN_C2PMSG_96', 'regMP1_SMN_C2PMSG_96_BASE_IDX',
    'regMP1_SMN_C2PMSG_97', 'regMP1_SMN_C2PMSG_97_BASE_IDX',
    'regMP1_SMN_C2PMSG_98', 'regMP1_SMN_C2PMSG_98_BASE_IDX',
    'regMP1_SMN_C2PMSG_99', 'regMP1_SMN_C2PMSG_99_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH0', 'regMP1_SMN_EXT_SCRATCH0_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH1', 'regMP1_SMN_EXT_SCRATCH10',
    'regMP1_SMN_EXT_SCRATCH10_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH11',
    'regMP1_SMN_EXT_SCRATCH11_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH12',
    'regMP1_SMN_EXT_SCRATCH12_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH13',
    'regMP1_SMN_EXT_SCRATCH13_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH14',
    'regMP1_SMN_EXT_SCRATCH14_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH15',
    'regMP1_SMN_EXT_SCRATCH15_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH16',
    'regMP1_SMN_EXT_SCRATCH16_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH17',
    'regMP1_SMN_EXT_SCRATCH17_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH18',
    'regMP1_SMN_EXT_SCRATCH18_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH19',
    'regMP1_SMN_EXT_SCRATCH19_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH1_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH2',
    'regMP1_SMN_EXT_SCRATCH20', 'regMP1_SMN_EXT_SCRATCH20_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH21', 'regMP1_SMN_EXT_SCRATCH21_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH22', 'regMP1_SMN_EXT_SCRATCH22_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH23', 'regMP1_SMN_EXT_SCRATCH23_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH24', 'regMP1_SMN_EXT_SCRATCH24_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH25', 'regMP1_SMN_EXT_SCRATCH25_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH26', 'regMP1_SMN_EXT_SCRATCH26_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH27', 'regMP1_SMN_EXT_SCRATCH27_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH28', 'regMP1_SMN_EXT_SCRATCH28_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH29', 'regMP1_SMN_EXT_SCRATCH29_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH2_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH3',
    'regMP1_SMN_EXT_SCRATCH30', 'regMP1_SMN_EXT_SCRATCH30_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH31', 'regMP1_SMN_EXT_SCRATCH31_BASE_IDX',
    'regMP1_SMN_EXT_SCRATCH3_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH4',
    'regMP1_SMN_EXT_SCRATCH4_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH5',
    'regMP1_SMN_EXT_SCRATCH5_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH6',
    'regMP1_SMN_EXT_SCRATCH6_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH7',
    'regMP1_SMN_EXT_SCRATCH7_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH8',
    'regMP1_SMN_EXT_SCRATCH8_BASE_IDX', 'regMP1_SMN_FPS_CNT',
    'regMP1_SMN_FPS_CNT_BASE_IDX', 'regMP1_SMN_IH_CREDIT',
    'regMP1_SMN_IH_CREDIT_BASE_IDX', 'regMP1_SMN_IH_SW_INT',
    'regMP1_SMN_IH_SW_INT_BASE_IDX', 'regMP1_SMN_IH_SW_INT_CTRL',
    'regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX', 'regMP1_SMN_PUB_CTRL',
    'regMP1_SMN_PUB_CTRL_BASE_IDX', 'regMPIO_FIRMWARE_FLAGS',
    'regMPIO_FIRMWARE_FLAGS_BASE_IDX']
